After the present invention has been brought to completion, the present inventors have investigated the known references about the following viewpoints A and B on the basis of the result of the invention. The viewpoint A is one wherein a potential at a semiconductor well in which an n channel type MOSFET or a p channel type MOSFET is formed, is biased in a weak forward direction with respect to a source potential. The viewpoint B is one wherein a potential at a semiconductor well in which an n channel type MOSFET or a p channel type MOSFET is formed, is biased in a backward direction with respect to a source potential.
As to the viewpoint A, the following publications have been found out.
(1) IEEE 1992 symposium on VLSI Technology Digest of Technical paper, pp 104–105,
(2) Unexamined Patent Publication No. Hei 6(1994)-21443,
(3) Unexamined Patent Publication No. Hei 6(1994)-216346,
(4) Unexamined Patent Publication No. Hei 3(1991)-23591,
(5) Unexamined Patent Publication No. Hei 1(1989)-206661,
(6) Unexamined Patent Publication No. Hei 3(1991)-136365, and
(7) Unexamined Patent Publication No. Hei 8(1996)-204140.
As to the viewpoint B, the following publications have been found out.
(8) Unexamined Patent Publication No. Hei 8(1996)-274620,
(9) Unexamined Patent Publication No. Hei 5(1993)-108194,
(10) Unexamined Patent Publication No. Hei 6(1994)-53496, and
(11) Unexamined Patent Publication No. Hei 6(1994)-89574.
A configuration wherein a back bias voltage of each MOSFET is changed, is common among the respective references. However, problems and effects to be solved by the application of back bias voltages to the MOSFETs vary widely. Even in the case of any of them, such ones as to expect problems, configurations and effects to be solved by the invention of the present application are not found.
The inventors of the present application have lead to the development of a novel method of setting back biases of a MOS circuit and a novel MOS integrated circuit both intended for the solution of such a technical problem that a high-speed operation and low power consumption are placed in a mutually contradictory relationship as in the case where when attempt is made to achieve the high-speed operation upon development of a MOS integrated circuit suitable for device scale-down and portability of an electronic device, the low power consumption increases correspondingly, whereas when priority is given to the low power consumption in reverse, the high-speed operation is sacrificed.
Thus, the present invention aims to provide a method of setting back biases of a MOS circuit wherein a speeding up and low power consumption have been implemented, and a MOS integrated circuit. Another object of the present invention is to provide a method of setting back biases of a MOS circuit wherein a speeding up and low power consumption have been implemented without complicating a manufacturing process. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.